How to build a self gating randomizer?
I need to build a self gating randomizer?
Here is an example of what I need.
The randomizer is being driven by an iterator
The randomizer outputs a 2, then it waits for 2 steps from the iterator before it outputs it's next value.
I need to do some kind of compare between the iterator and itself + the random value so I can filter out 2 iterator steps and trigger a new random of the third.
How could I make a randomizer that waits a certain number of iteration steps before it triggers a new value?
Answers
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I need to build a self gating randomizer?
Michael, in MRC I use Sharl with a NOT logic from a seq clock.
How could I make a randomizer that waits a certain number of iteration steps before it triggers a new value?
Driven by the same procedere as above. Send the event to the randomizer.
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I looked into your midi instrument, but I didn't fully understand what the not module was doing, could you explain this to me?
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maybe a chain of iterators
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Simple way to solve your example would be to have a countdown counter, and use the random value to set the counter... so if the random value is 3, then the counter is set to 3, and counts down 1 per tick. When it hits zero, it triggers the random generator again for another value
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Michael, Sharl is driving by a seq clock with random 2 directions.
Sharl (Change after response logic zero = Charlz, renamed by Catman Dude to Sharl) gives out an event if logic zero is passed.
You can send like me this event to a random trigger or use it direct.
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I tried this exact approach but it had some massive issues, maybe I need to revisit this method.
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What issues?
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It's turning out like this...
Here is the structure.
Here are the output values.
Top row is the iteration count, second row is the random output numbers, third row is the countdown numbers.
If it were counting down properly then the bottom row should be outputting 2-1-0, 2-1-0, 3-2-1-0, 1-0.
The second row should have output a 2 at the start, a new number in the third space if it had reached zero properly and so on, but it only output the 4 in space 6
The duplicate 1's in the second and third place are an error, and the 2 to 3 in 4th and 5th place are an error, the 3 to 0 in spaces 5 & 6 and the double 3's in spaces 7 & 8 as well as the three 1's in a row and the 2 coming after a 1 are all errors.
Any ideas on this?
Thanks.
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Don't like those orange wires
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Something like this?
The plus 1 and the init to 1 are because this simple version only checks for ==0, so if it gets negative, it goes forever (until a 32bit in wrap anyway)... would be easy to do a more complex version where it only counts down when positive.
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This is doing the trick, I always overlook the read and write modules unless I'm doing wavetable data memory types of stuff, can't see the forrest through the trees sometimes.
Thanks a ton.
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Micheal, do you know what a flip flop is? It changes states each time it is triggered. You might say it produces a square wave of 1/2 the frequency. So every 2 steps it with switch starts. Follow it with an edge triggered module and it should work if I have have your question pictured correctly. Or perhaps a single edge trigger device since you getting a new number each time. No comparator necessary, use a latch that is edge triggered and latch whatever number you want.
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To paste an .rcc macro don't works
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