is it possible to delay events in Core in order to convert simple 0/1 logic gates to triggers? I've tried using 1-sample delays (and latch[-1]), flipping the output of that and merging with the original signal, but I can't seem to get the event delayed without using a module that doesn't require it to already exist. I get that event flow in core is simultaneous, so does that mean I need to break out of core to do this? just something simple like the Hold module in Primary is what I'm looking to reproduce