Previous value

Here is a verry simpe example of Alpha Forever , and why I keep struggling with core forever .

I compare the previous value against the current value , source square wave .

When routing the input square into the false input , I get a perfect one unit impulse spike .
This works a bit different compared to reaktor since the comparitor also function as a switch. ( thus a combined comparator and router )
However , doing the exact same thing in reaktor ( at least to me ) I don't get the desired result

For previous value I use a write-read with the obc connection reversed , this delays the input by one sample
Then using the comparitor and switch

I just get a square at it's output

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gentleclockdivider

These two structures are identical

Why doesn't core give me a unit spike ?

My point being , comparing (=) a signal that has a delayed value to a non delayed signal should give a false output when the square goes from low to high = 1 unit sample spike .
Fact that I am ( most probably ) overseeing something to an otherwise verry simple task makes it far from intuitive

p.s. , why is the image scaling on this forum so horrible ( cutting expenses …? )

gentleclockdivider

Let's dumb it down

Do it in primary , boolean output of comparitor multied by input signa ( square ) gives a unit spike ..nice

Rebuild in core ..finnaly managed .

KoaN

I think you understood in your last try but in this example "your first pic" when the router goes up the value just hangs at the lower input…you need a system of pushing through your 0 and 1 yes,this is how the core router works.

The router in primary does that too but when using a primary comparator you don't need any router,it ouputs 0 or 1.

colB

If the input is a -1 to 1 naïve pulse wave, then this will give a 1 sample pulse each time the input changes:

If the input is anti-aliased, then it will kind of work, but won't be 'correct' (a single sample of value 1), but then neither will your last version. It's generally a more complex problem at that point that might require different solutions depending on the context.

The beauty of core is that you have full control. It's events + math not 'signals', and you can choose exactly what compromises you are willing to accept.

gentleclockdivider

I'm aware of the simple subtraction method .
That was not what Iwas struggling with ;)

gentleclockdivider

Getting thehang of it
Converting a gate to an impulse trigger

gentleclockdivider

This works
Subtracting delayed version fr og input ( which is a gate signal btw )

But adding a divide before it does not , so gate is always 1 regardless velocity value

gentleclockdivider

Primary has no issue with the divide

gentleclockdivider

So it works if I put a denormal before the ( lower input ) of divide
Is this because the z-1 has difficulties with 0/0 ?
Why does DNC after the divide solves this ?

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