Even without sr.c we get an infinte counter How is this possible , since the feedback loop ( uppr adder ) it's not triggred by sr.c ?
I'd guess what's happening here is due to the feedback loop (hence the orange wires), in which case the core compiler implicitly inserts a Z^-1 (i.e., clocked @ the sample rate). I suspect you probably ought to replace the lower adder with an xa+b module.
Are you trying to do something specific that the factory core counter won't do?
I know how it works with mem, read modules etc… and implicit versus explicit feedback loops . But never thought the aritm. modules are constantly processed Interesting , here obc connection is reversed
So an implicit feedback automatically( with no mem read-write) inserts a hidden sr.c ?
But never thought the aritm. modules are constantly processed
They're not.
When you create a feedback loop without an explicit z^-1 module, Reaktor inserts an implicit one and turns the wire orange as a warning that this is happening. Z^-1 is clocked at audio rate.
Big Gnome already explained this in the first reply you got.
Okay , but it's confusing that the automatically inserted implicit one is also automatically clocked at SR.C. and thus triggering the adder .
I guess that's why the mantra : "use latches whenever possible " applies .
If you want a mantra that fits this situation, I would say:
Orange wires are a warning. Always use explicit z^-1 modules for feedback
