hello forum,
is it possible that the delay module has some kind of memory that influences incoming values? if i understood correctly, the output value should be identical to the input value - just with a time delay.
in this case, the signal at the output of the delay module differs significantly from that at the input.
i'm trying to build a shepard-scale: 8 sine oscillators build a "generator" and 16 generators build one sound module. there are 3 of these modules in total.
each of the modules has different overtone structures for their generators and a time factor (8000ms, 12000ms, 16000ms) which determines when each of the 16 generators starts: generator 1 at time factor * 0, generator 2 at time factor * 1, ... generator 16 at time factor *16).
everything works fine.
the last hurdle is to start the complete construct at a time x, will say in a state in which all oscillators are somewhere in the middle of the scale in order to conceal the otherwise audible structure of the individual parts.
the counter output influences 2 factors of the generator: it adds a calculated offset to the ramp oscillator in round 1 (for starting inside the scale), and it decides whether the delay module is taken into account. the delay should be ignored in round 1 so that all generators are online at the same time.
this works great for the first generator. from the second generator onwards there is a problem. after round 1 it doesn't start again from the beginning, but again towards the end. in the third round there is a reset in the first quarter. after this, everything returns to normal.
i discovered, that from round 1 there is a completely different value at the output of the delay module than at the input - and that is probably the problem. how does this change in value come about and how can it be prevented?
the screenshot shows generator 2 of the first module and the in-and output of the delay-module.
thanks in advance,
bernd
